Runtime resource management for lifetime extension in multi-core systems

The availability of numerous, possibly heterogeneous, processing resources in multi-core systems allows one to exploit them to optimize performance and/or power/energy consumption. In particular, strategies have been defined to map and schedule tasks on the system resources, with the aim of optimizing the adopted figure of merit, at design time, if the working context is known in advance and relatively stable, at run time when facing changing/unpredictable working conditions. However, it is important to be aware that such strategies may have an impact on the overall lifetime of the system because of aging and wear-out mechanisms. Therefore such management strategies, generally adopted for handling performance and power consumption aspects, should be enhanced in order to consider such issues. Furthermore, specific Dynamic Reliability Management (DRM) policies have been devised to deal with lifetime issues in multi-core systems, acting mainly on the workload distribution (and eventually on architectural knobs, such as voltage/frequency scaling) to mitigate the stress caused by the running applications. Here we will focus on DRM strategies, whose goal is pursuing the improvement of lifetime reliability by means of load distribution policies that identify the resource where to map a new application entering the system, or where to periodically migrate tasks to balance stress. More precisely, a selection of state-of-the-art solutions will be presented and analysed, with respect to the achieved expected lifetime, evaluated when considering the first failure as well as the sequence of failures leading to the system being unable to fulfill the user's performance of service requirements

A configurable board-level adaptive incremental diagnosis technique based on decision trees

Functional diagnosis for complex electronic boards is a time-consuming task that requires big expertise to the diagnosis engineers. In this paper we propose a new engine for board-level adaptive incremental functional diagnosis based on decision trees. The engine incrementally selects the tests that have to be executed and based on the test outcomes it automatically stops the diagnosis as soon as one or more faulty candidates can be identified, thus allowing to reduce the number of executed tests. Moreover, we propose a configurable early stop condition for the engine that allows to further reduce the number of executed tests leveraging the diagnosis accuracy. The effectiveness of the proposed approach has been assessed using a set of synthetic but realistic boards and three industrial boards

Combined on-line lifetime-energy optimization for asymmetric multicores

In this paper we present an architectural and on-line resource management solution to optimize lifetime reliability of asymmetric multicores while minimizing the system energy consumption, targeting both single nodes (multicores) as well as multiple ones (cluster of multicores). The solution exploits the different characteristics of the computing resources to achieve the desired performance while optimizing the lifetime/energy trade-off. The experimental results show that a combined optimization of energy and lifetime allows for achieving an extended lifetime (similar to the one pursued by lifetime-only optimization solutions) with a marginal energy consumption detriment (less than 2%) with respect to energy-aware but aging-unaware systems

Performance Optimization on big.LITTLE Architectures:A Memory-latency Aware Approach

The energy demands of modern mobile devices have driven a trend towards heterogeneous multi-core systems which include various types of core tuned for performance or energy efficiency, offering a rich optimization space for software. On such systems, data coherency between cores is automatically ensured by an interconnect between processors. On some chip designs the performance of this interconnect, and by extension of the entire CPU cluster, is highly dependent on the software's memory access characteristics and on the set of frequencies of each CPU core. Existing frequency scaling mechanisms in operating systems use a simple load-based heuristic to tune CPU frequencies, and so fail to achieve a holistically good configuration across such diverse clusters. We propose a new adaptive governor to solve this problem, which uses a simple trained hardware model of cache interconnect characteristics, along with real-time hardware monitors, to continually adjust core frequencies to maximize system performance. We evaluate our governor on the Exynos5422 SoC, as used in the Samsung Galaxy S5, across a range of standard benchmarks. This shows that our approach achieves a speedup of up to 40%, and a 70% energy saving, including a 30% speedup in common mobile applications such as video decoding and web browsing

Energy Optimization and Management of Demand Response Interactions in a Smart Campus

The proposed framework enables innovative power management in smart campuses, integrating local renewable energy sources, battery banks and controllable loads and supporting Demand Response interactions with the electricity grid operators. The paper describes each system component: the Energy Management System responsible for power usage scheduling, the telecommunication infrastructure in charge of data exchanging and the integrated data repository devoted to information storage. We also discuss the relevant use cases and validate the framework in a few deployed demonstrators

Quality of Service Driven Runtime Resource Allocation in Reconfigurable HPC Architectures

Heterogeneous System Architectures (HSA) are gaining importance in the High Performance Computing (HPC) domain due to increasing computational requirements coupled with energy consumption concerns, which conventional CPU architectures fail to effectively address. Systems based on Field Programmable Gate Array (FPGA) recently emerged as an effective alternative to Graphical Processing Units (GPUs) for demanding HPC applications, although they lack the abstractions available in conventional CPU-based systems. This work tackles the problem of runtime resource management of a system using FPGA-based co-processors to accelerate multi-programmed HPC workloads. We propose a novel resource manager able to dynamically vary the number of FPGAs allocated to each of the jobs running in a multi-accelerator system, with the goal of meeting a given Quality of Service metric for the running jobs measured in terms of deadline or throughput. We implement the proposed resource manager in a commercial HPC system, evaluating its behavior with representative workloads

CASTOR: a computer aided system testability optimizer

CASTOR is an expert module that solves testability problems detected in a hardware design by advising the designer on the application of Design for Testabilily techniques. The system evaluates all possible solutions and implements the most economic one in terms of overheads. The optimal solution is obtained by applying a Branch and Bound strategy to carry out the exhaustive search of the best solution, optimizing system resources. A suitable cost function is used to quantify the effects of the application of each DfT technique to the circuit examined

Fault Classification for SRAM-Based FPGAs in theSpace Environment for Fault Mitigation

This letter proposes a classification algorithm to discriminate between recoverable and not recoverable faults occurring in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), with the final aim of devising a methodology to enable the exploitation of these devices also in space applications, typically characterized by long mission times, where permanent faults become an issue. By starting from a characterization of the radiation effects and aging mechanisms, we define a controller able to classify such faults and consequently to apply the appropriate mitigation strategy